Packaging Overview
Summary
This chapter covers the following topics:•••
Introduction
Device/Package Combinations and Maximum I/OsPin Definitions
Introduction
This section describes the pinouts for Virtex®-5 devices in the 1.00mm pitch flip-chip fine-pitch BGA packages.
Virtex-5 devices are offered exclusively in high performance flip-chip BGA packages that are optimally designed for improved signal integrity and jitter. Package inductance is minimized as a result of optimal placement and even distribution as well as an increased number of Power and GND pins.
All of the devices supported in a particular package are pinout compatible and are listed in the same table (one table per package). Pins that are not available for the smaller devices are listed in the “No Connects” column of each table.
For Virtex-5Q devices, the EF package is offered. The only difference between an EF and an FF package is that the discrete substrate capacitors on the EF package are coated with epoxy. The coating is comprised of an undercoat epoxy that is dispensed under the
capacitors and an overcoat epoxy that is dispensed over the top of the capacitors. All other package construction characteristics of the EF matches that of the FF package. The EF package changes are noted in Chapter4, “Mechanical Drawings.”
Each device is split into eight or more I/O banks to allow for flexibility in the choice of I/O standards (see UG190: Virtex-5 FPGA User Guide). Global pins, including JTAG, configuration, and power/ground pins, are listed at the end of each table. Table1-7 provides definitions for all pin types.
For information on package electrical characteristics and how the characteristics are measured, refer to UG112: Device Package User Guide found on the Xilinx website.For the latest Virtex-5 FPGA pinout information, check the Xilinx website for any updates to this document.
Virtex-5 FPGA Packaging and Pinout Specificatio
Chapter 1:Packaging Overview
Device/Package Combinations and Maximum I/Os
Table1-1 shows the maximum number of user I/Os possible in Virtex-5 FPGA flip-chip packages. FF denotes flip-chip fine-pitch BGA (1.00 mm pitch).
Table 1-3:I/O ChannelsMGTRXPMGTRXNMGTTXPMGTTXN
Number of GTP Transceiver I/O Channels/Device
Device
LX20TLX30T(1)SX35TLX50T(2)SX50T(3)LX85TSX95TLX110TLX155TLX220TSX240TLX330T
4444
4 or 84 or 84 or 84 or 8
8888
8 or 128 or 128 or 128 or 12
8 or 128 or 128 or 128 or 12
12121212
16161616
16161616
16161616
16161616
24242424
24242424
Virtex-5 FPGA Packaging and Pinout Specification
Pin Definitions
Table 1-7:Virtex-5 FPGA Pin Definitions (Continued)
Direction
Description
Pin Name
Dedicated Configuration Pins(1)CCLK_0CS_B_0D_IN_0DONE_0
Input/OutputInputInputInput/Output
Configuration clock. Output and input in Master mode or Input in Slave mode.In SelectMAP mode, this is the active-low Chip Select signal. In bit-serial modes, D_IN is the single-data input.
DONE is a bidirectional signal with an optional internal pull-up resistor. As an output, this pin indicates completion of the configuration process. As an input, a Low level on DONE can be configured to delay the start-up sequence.In SelectMAP mode, BUSY controls the rate at which configuration data is loaded.
In bit-serial modes, DOUT gives preamble and configuration data to down-stream devices in a daisy chain.
Enable I/O pullups during configuration
D_OUT_BUSY_0Output
HSWAPEN_0INIT_B_0
M0_0, M1_0, M2_0PROGRAM_BRDWR_B_0TCK_0TDI_0TDO_0TMS_0DXP_0, DXN_0 Reserved PinsRSVDFLOATOther PinsGNDVBATT_0VCCAUXVCCINTVCCO_#(2)
Input
When Low, this pin indicates that the configuration memory is being cleared.
Bidirectional
When held Low, the start of configuration is delayed. During configuration, a
(open-drain)
Low on this output indicates that a configuration data error has occurred.
InputInputInputInputInputOutputInputN/A
Configuration mode selection
Active Low asynchronous reset to configuration logic. This pin has a permanent weak pull-up resistor.
In SelectMAP mode, this is the active-low Write Enable signal.Boundary-Scan Clock.Boundary-Scan Data Input.Boundary-Scan Data Output.Boundary-Scan Mode Select.
Temperature-sensing diode pins (Anode: DXP; Cathode: DXN).
N/AN/A
Reserved pins—must be tied to ground.
Do not connect this pin to the board. Leave floating.
N/AN/AN/AN/AN/A
Ground.
Decryptor key memory backup supply; this pin should be tied to VCC or GND.Power-supply pins for auxiliary circuits.Power-supply pins for the internal core logic.Power-supply pins for the output drivers (per bank).
Virtex-5 FPGA Packaging and Pinout Specificatio
FF323 Package—LX20T and LX30T
Virtex-5 FPGA Packaging and Pinout Specificatio
Chapter 2:Pinout Tables
Virtex-5 FPGA Packaging and Pinout Specification
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