library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity rs232 is
Port(clk,rx,reset: in STD_LOGIC;
tx : out STD_LOGIC;
cnt : out integer range 0 to 31;
dateout:out std_logic_vector(7 downto 0));
end rs232;
architecture Behavioral of rs232 is
signal div,div3:std_logic_vector(11 downto 0);
signal clk1,aw1,clk3 :std_logic;
signal date_out: std_logic_vector(9 downto 0);
Signal busy :std_logic ;
Signal Enable :std_logic :='0';
Signal Hold :std_logic :='0';
Signal N :std_logic_vector(0 to 2) :=\"000\";
begin
busy<=Enable and Hold;
process(reset,rx)
begin
if reset='0' then
Hold<='0';
elsif falling_edge(rx) then
Hold<='1';
end if;
end process;
process(clk)
begin
if reset='0' then
aw1<='0';
div<=(others=>'0');
elsif rising_edge(clk) then
div <=div+1;
if div=519 then
div<=(others=>'0');
aw1<='1';
else aw1<='0';
end if;
end if;
end process;
process(aw1)
begin
if rising_edge(aw1) then
clk1<=not clk1;
end if;
end process;
process(clk)
begin
if reset='0' then
clk3<='0';
div3<=(others=>'0');
elsif rising_edge(clk) then
div3 <=div3+1;
if div3=347 then
div3<=(others=>'0');
clk3<='1';
else clk3<='0';
end if;
end if;
end process;
process(clk3,reset)
variable m:integer range 0 to 2 :=0;
begin
if reset='0' then
m:=0;
elsif(rising_edge(clk3) and N(m)<=rx;
if m=2 then
m:=0;
else
m:=m+1;
end if;
end if;
end process;
process(clk1,reset)
busy='0' ) then
variable Num:integer range 0 to 9 :=0;
begin
if reset='0' then
Enable<='0' ; Num:=0;
elsif (rising_edge(clk1) and busy='0') then
date_out(Num)<=(N(0) and N(1)) or (N(1) and N(2)) or (N(0) and N(2));
if Num=9 then
Enable<='1'; Num:=0;
else
Num:=Num+1;
Enable<='0';
end if;
end if;
end process;
process(Enable,date_out)
variable cnts:integer range 0 to 31 :=0;
begin
cnt<= cnts;
if rising_edge(Enable) then
dateout<=date_out(8 downto 1);
if cnts=31 then
cnts:=0;
else
cnts:=cnts+1;
end if;
end if;
end process;
end Behavioral;
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