•Low-voltage and Standard-voltage Operation
–5.0 (VCC = 4.5V to 5.5V)–2.7 (VCC = 2.7V to 5.5V)–1.8 (V•CC = 1.8V to 3.6V)Internally Organized 65,536 x 8•2-wire Serial Interface
•Schmitt Triggers, Filtered Inputs for Noise Suppression•Bidirectional Data Transfer Protocol
•1 MHz (5V), 400 kHz (2.7V) and 100 kHz (1.8V) Compatibility•Write Protect Pin for Hardware and Software Data Protection•128-byte Page Write Mode (Partial Page Writes Allowed)•Self-timed Write Cycle (5 ms Typical)•
High Reliability
–Endurance: 100,000 Write Cycles –Data Retention: 40 Years–ESD Protection: >4000V
•Automotive Grade and Extended Temperature Devices Available
•
8-pin PDIP and 20-pin JEDEC SOIC, 8-pin LAP, and 8-ball dBGATM Packages
Description
The AT24C512 provides 524,288 bits of serial electrically erasable and programmableread only memory (EEPROM) organized as 65,536 words of 8 bits each. The device’scascadable feature allows up to 4 devices to share a common 2-wire bus. The deviceis optimized for use in many industrial and commercial applications where low-powerand low-voltage operation are essential. The devices are available in space-saving8-pin PDIP, 20-pin JEDEC SOIC, 8-pin Leadless Array (LAP), and 8-ball dBGA pack-ages. In addition, the entire family is available in 5.0V (4.5V to 5.5V), 2.7V (2.7V to5.5V) and 1.8V (1.8V to 3.6V) versions.
Pin Configurations
8-pin PDIP
Pin NameFunctionA018VCCA0 - A1Address InputsA127WPSDASerial DataNC36SCLGND45SDASCLSerial Clock InputWPWrite ProtectNC
No Connect8-pin Leadless Array
VCC81A020-pin SOIC
WP72A1SCL63NCSDA54GNDA0120VCCA1219WPBottom ViewNC318NCNC417NC8-ball dBGANC516NCNC615NCVCC81A0NC714NCWP72A1NC813NCSCL63NCNC912SCLSDA54GNDGND1011SDABottom View
2-wire Serial EEPROM512K (65,536 x 8)AT24C512 Rev. 1116D–07/001
Absolute Maximum Ratings*
Operating Temperature..................................-55°C to +125°CStorage Temperature.....................................-65°C to +150°CVoltage on Any Pin
with Respect to Ground.....................................-1.0V to +7.0VMaximum Operating Voltage..........................................6.25VDC Output Current........................................................5.0 mA
*NOTICE:
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam-age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Block Diagram
Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positiveedge clock data into each EEPROM device and negativeedge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional forserial data transfer. This pin is open-drain driven and maybe wire-ORed with any number of other open-drain or opencollector devices.
DEVICE/PAGE ADDRESSES (A1, A0): The A1 and A0pins are device address inputs that are hardwired or left notconnected for hardware compatibility with AT24C128/256.When the pins are hardwired, as many as four 512Kdevices may be addressed on a single bus system (deviceaddressing is discussed in detail under the DeviceAddressing section). When the pins are not hardwired, thedefault A1 and A0 are zero.2
WRITE PROTECT (WP): The write protect input, when tiedto GND, allows normal write operations. When WP is tiedhigh to VCC, all write operations to the memory are inhib-ited. If left unconnected, WP is internally pulled down toGND. Switching WP to VCC prior to a write operation cre-ates a software write protect function.
Memory Organization
AT24C512, 512K SERIAL EEPROM: The 512K is inter-nally organized as 512 pages of 128-bytes each. Randomword addressing requires a 16-bit data word address.
AT24C512
AT24C512
Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V.
SymbolCI/OCINNote:
Test Condition
Input/Output Capacitance (SDA)Input Capacitance (A0, A1, SCL)
1.This parameter is characterized and is not 100% tested.
Max86
UnitspFpF
ConditionsVI/O = 0VVIN = 0V
DC Characteristics
Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +1.8V to +5.5V, TAC = 0°C to +70°C,VCC = +1.8V to +5.5V (unless otherwise noted).
SymbolVCC1VCC2VCC3ICC1ICC2ISB1
ParameterSupply VoltageSupply VoltageSupply VoltageSupply CurrentSupply CurrentStandby Current(1.8V option)Standby Current(2.7V option)Standby Current(5.0V option)
Input Leakage CurrentOutput Leakage Current
Input Low Level(1)Input High Level(1)Output Low LevelOutput Low Level1.
VCC = 3.0VVCC = 1.8V
IOL = 2.1 mAIOL = 0.15 mA
VCC = 5.0VVCC = 5.0VVCC = 1.8VVCC = 3.6VVCC = 2.7VVCC = 5.5VVCC = 4.5 - 5.5VVIN = VCC or VSSVOUT = VCC or VSS
-0.6VCC x 0.7
READ at 400 kHzWRITE at 400 kHzVIN = VCC or VSS
Test Condition
Min1.82.74.5
1.02.0Typ
Max3.65.55.52.03.00.22.00.66.06.0
0.100.05
3.03.0VCC x 0.3VCC + 0.50.40.2
UnitsVVVmAmA
µAµA
ISB2ISB3ILIILOVILVIHVOL2VOL1Note:
VIN = VCC or VSSVIN = VCC or VSS
µAµAµA
VVVV
VIL min and VIH max are reference only and are not tested.
3
AC Characteristics
Applicable over recommended operating range from TA = -40°C to +85°C, VCC = +1.8V to +5.5V, CL = 100 pF (unless oth-erwise noted). Test conditions are listed in Note 2.
1.8-volt
SymbolfSCLtLOWtHIGHtAAtBUFtHD.STAtSU.STAtHD.DATtSU.DATtRtFtSU.STOtDHtWR
Endurance(1)Notes:
Parameter
Clock Frequency, SCLClock Pulse Width LowClock Pulse Width HighClock Low to Data Out Valid
Time the bus must be free before a new transmission can start(1)Start Hold TimeStart Set-up TimeData In Hold TimeData In Set-up TimeInputs Rise Time(1)Inputs Fall Time(1)Stop Set-up TimeData Out Hold TimeWrite Cycle Time5.0V, 25°C, Page Mode
100K
1.This parameter is characterized and is not 100% tested.2.AC measurement conditions:
RL (connects to VCC): 1.3KΩ (2.7V, 5V), 10KΩ (1.8V)Input pulse voltages: 0.3VCC to 0.7VCCInput rise and fall times: ≤50ns
Input and output timing reference voltages: 0.5VCC
4.7100
20
100K
4.74.00.14.74.04.70200
1.0300
0.650
10
100K
4.5
Min
Max100
1.31.00.051.30.60.60100
0.3300
0.2550
10
0.9
2.7-voltMin
Max400
0.60.40.050.50.250.250100
0.31000.555.0-voltMin
Max1000
UnitskHz
µsµsµsµsµsµsµs
ns
µs
ns
µs
nsmsWrite Cycles
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is nor-mally pulled high with an external device. Data on the SDApin may change only during SCL low time periods (refer toData Validity timing diagram). Data changes during SCLhigh periods will indicate a start or stop condition as definedbelow.
START CONDITION: A high-to-low transition of SDA withSCL high is a start condition which must precede any othercommand (refer to Start and Stop Definition timing dia-gram).
STOP CONDITION: A low-to-high transition of SDA withSCL high is a stop condition. After a read sequence, thestop command will place the EEPROM in a standby powermode (refer to Start and Stop Definition timing diagram).
ACKNOWLEDGE: All addresses and data words are seri-ally transmitted to and from the EEPROM in 8-bit words.The EEPROM sends a zero during the ninth clock cycle toacknowledge that it has received each word.
STANDBY MODE: The AT24C512 features a low powerstandby mode which is enabled: a) upon power-up and b)after the receipt of the STOP bit and the completion of anyinternal operations.
MEMORY RESET: After an interruption in protocol, powerloss or system reset, any 2-wire part can be reset by follow-ing these steps:
(a) Clock up to 9 cycles, (b) look for SDA high in each cyclewhile SCL is high and then (c) create a start condition asSDA is high.
4
AT24C512
AT24C512
Bus Timing (SCL: Serial Clock, SDA: Serial Data I/O)
Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O)
(1)Note:1.
The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
5
Data Validity
Start and Stop Definition
Output Acknowledge
6
AT24C512
AT24C512
Device Addressing
The 512K EEPROM requires an 8-bit device address wordfollowing a start condition to enable the chip for a read orwrite operation (refer to Figure 1). The device address wordconsists of a mandatory one, zero sequence for the firstfive most significant bits as shown. This is common to all 2-wire EEPROM devices.
The 512K uses the two device address bits A1, A0 to allowas many as four devices on the same bus. These bits mustcompare to their corresponding hardwired input pins. TheA1 and A0 pins use an internal proprietary circuit thatbiases them to a logic low condition if the pins are allowedto float.
The eighth bit of the device address is the read/write opera-tion select bit. A read operation is initiated if this bit is highand a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM willoutput a zero. If a compare is not made, the device willreturn to a standby state.
DATA SECURITY: The AT24C512 has a hardware dataprotection scheme that allows the user to write protect thewhole memory when the WP pin is at VCC.
data word address will “roll over” and previous data will beoverwritten. The address “roll over” during write is from thelast byte of the current page to the first byte of the samepage.
ACKNOWLEDGE POLLING: Once the internally-timedwrite cycle has started and the EEPROM inputs are dis-abled, acknowledge polling can be initiated. This involvessending a start condition followed by the device addressword. The read/write bit is representative of the operationdesired. Only if the internal write cycle has completed willthe EEPROM respond with a zero, allowing the read orwrite sequence to continue.
Read Operations
Read operations are initiated the same way as write opera-tions with the exception that the read/write select bit in thedevice address word is set to one. There are three readoperations: current address read, random address readand sequential read.
CURRENT ADDRESS READ: The internal data wordaddress counter maintains the last address accessed dur-ing the last read or write operation, incremented by one.This address stays valid between operations as long as thechip power is maintained. The address “roll over” duringread is from the last byte of the last memory page, to thefirst byte of the first page.
Once the device address with the read/write select bit setto one is clocked in and acknowledged by the EEPROM,the current address data word is serially clocked out. Themicrocontroller does not respond with an input zero butdoes generate a following stop condition (refer to Figure 4).RANDOM READ: A random read requires a “dummy” bytewrite sequence to load in the data word address. Once thedevice address word and data word address are clocked inand acknowledged by the EEPROM, the microcontrollermust generate another start condition. The microcontrollernow initiates a current address read by sending a deviceaddress with the read/write select bit high. The EEPROMacknowledges the device address and serially clocks outthe data word. The microcontroller does not respond with azero but does generate a following stop condition (refer toFigure 5).
SEQUENTIAL READ: Sequential reads are initiated byeither a current address read or a random address read.After the microcontroller receives a data word, it respondswith an acknowledge. As long as the EEPROM receives anacknowledge, it will continue to increment the data wordaddress and serially clock out sequential data words. Whenthe memory address limit is reached, the data wordaddress will “roll over” and the sequential read will con-tinue. The sequential read operation is terminated whenthe microcontroller does not respond with a zero but doesgenerate a following stop condition (refer to Figure 6).
Write Operations
BYTE WRITE: A write operation requires two 8-bit dataword addresses following the device address word andacknowledgment. Upon receipt of this address, theEEPROM will again respond with a zero and then clock inthe first 8-bit data word. Following receipt of the 8-bit dataword, the EEPROM will output a zero. The addressingdevice, such as a microcontroller, then must terminate thewrite sequence with a stop condition. At this time theEEPROM enters an internally-timed write cycle, tWR, to thenonvolatile memory. All inputs are disabled during this writecycle and the EEPROM will not respond until the write iscomplete (refer to Figure 2).
PAGE WRITE: The 512K EEPROM is capable of 128-bytepage writes.
A page write is initiated the same way as a byte write, butthe microcontroller does not send a stop condition after thefirst data word is clocked in. Instead, after the EEPROMacknowledges receipt of the first data word, the microcon-troller can transmit up to 127 more data words. TheEEPROM will respond with a zero after each data wordreceived. The microcontroller must terminate the pagewrite sequence with a stop condition (refer to Figure 3).The data word address lower 7 bits are internally incre-mented following the receipt of each data word. The higherdata word address bits are not incremented, retaining thememory page row location. When the word address, inter-nally generated, reaches the page boundary, the followingbyte is placed at the beginning of the same page. If morethan 128 data words are transmitted to the EEPROM, the
7
Figure 1. Device Address
Figure 2. Byte Write
Figure 3. Page Write
Figure 4. Current Address Read
8
AT24C512
AT24C512
Figure 5. Random Read
Figure 6. Sequential Read
9
Ordering Information
tWR (max)(ms)
10
ICC (max)(µA)3000
ISB (max)(µA)6.0
fMAX(kHz)1000
Ordering CodeAT24C512C1-10CCAT24C512-10PCAT24C512-10UC AT24C512W1-10SCAT24C512C1-10CIAT24C512-10PIAT24C512-10UIAT24C512W1-10SIAT24C512C1-10CC-2.7AT24C512-10PC-2.7AT24C512-10UC-2.7AT24C512W1-10SC-2.7AT24C512C1-10CI-2.7AT24C512-10PI-2.7AT24C512-10UI-2.7AT24C512W1-10SI-2.7AT24C512C1-10CC-1.8AT24C512-10PC-1.8AT24C512-10UC-1.8AT24C512W1-10SC-1.8AT24C512C1-10CI-1.8AT24C512-10PI-1.8AT24C512-10UI-1.8AT24C512W1-10SI-1.8
Package8C18P38U320S8C18P38U320S8C18P38U320S8C18P38U320S8C18P38U320S8C18P38U320S
Operation RangeCommercial(0°C to 70°C)
30006.01000
Industrial(-40°C to 85°C)
1015000.6400
Commercial(0°C to 70°C)
15000.6400
Industrial(-40°C to 85°C)
108000.2100
Commercial(0°C to 70°C)
8000.2100
Industrial(-40°C to 85°C)
Package Type
8C18P38U320S
8-lead, 0.300\" Wide, Leadless Array Package (LAP)8-lead, 0.300\" Wide, Plastic Dual In-line Package (PDIP)8-ball, die Ball Grid Array Package (dBGA)
20-lead, 0.300\" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
Options
Blank-2.7-1.8
Standard Operation (4.5V to 5.5V)Low-voltage (2.7V to 5.5V)Low-voltage (1.8V to 3.6V)
10
AT24C512
AT24C512
Packaging Information
8C1, 8-lead, 0.300\" Wide,Leadless Array Package (LAP)Dimensions in Millimeters and (Inches)*8P3, 8-lead, 0.300\" Wide,Plastic Dual In-line Package (PDIP)Dimensions in Inches and (Millimeters)JEDEC STANDARD MS-001 BA.400 (10.16).355 (9.02)PIN1.280 (7.11).240 (6.10).037 (.940).027 (.690)TOP VIEWSIDEVIEW5.10 (0.201)4.90 (0.193).300 (7.62) REF8.10 (0.319)7.90 (0.311)BOTTOM VIEW1.32 (0.052)1.22 (0.048)874.76 (0.187)4.66 (0.183)650.34 (0.013)0.24 (0.009)1.22 (0.048)1.12 (0.044)12340.92 (0.036)0.82 (0.032)0.95 (0.037)0.85 (0.033)1.14 (0.045)0.94 (0.037)0.38 (0.015)0.30 (0.012).210 (5.33) MAXSEATINGPLANE.150 (3.81).115 (2.92).070 (1.78).045 (1.14).100 (2.54) BSC.015 (.380) MIN.022 (.559).014 (.356).325 (8.26).300 (7.62).012 (.305).008 (.203)0REF15.430 (10.9) MAX* Controlling dimension: millimeters8U3, 8-ball, die Ball Grid Array Package (dBGA)Dimensions in Millimeters and (Inches)*20S, 20-lead, 0.300\" Wide,Plastic Gull Wing Small Outline (JEDEC SOIC)Dimensions in Inches and (Millimeters)TOP VIEW3.40 (0.134)0.020 (0.508)0.013 (0.330)PIN 10.299 (7.60)0.420 (10.7)0.291 (7.39)0.393 (9.98)5.21 (0.205).050 (1.27) BSCSIDE VIEWBOTTOM VIEW0.38 (0.015)0.513 (13.0)0.497 (12.6)0.105 (2.67)0.092 (2.34)87120.012 (0.305)0.003 (0.076)60.75 (0.029)51.48 (0.058)0.75 (0.029)340REF80.013 (0.330)0.009 (0.229)1.33 (0.052)0.52 (0.020)0.035 (0.889)0.015 (0.381)* Controlling dimension: millimeters11
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