74LVT16245资料

74LVT16245 • 74LVTH16245 Low Voltage 16-Bit Transceiver with 3-STATE OutputsJanuary 1999Revised June 2005

74LVT16245 • 74LVTH16245

Low Voltage 16-Bit Transceiver with 3-STATE Outputs

General Description

The LVT16245 and LVTH16245 contain sixteen non-invert-ing bidirectional buffers with 3-STATE outputs and isintended for bus oriented applications. The device is bytecontrolled. Each byte has separate control inputs whichcan be shorted together for full 16-bit operation. The T/Rinputs determine the direction of data flow through thedevice. The OE inputs disable both the A and B ports byplacing them in a high impedance state.

The LVTH16245 data inputs include bushold, eliminatingthe need for external pull-up resistors to hold unusedinputs.

These non-inverting transceivers are designed for low-volt-age (3.3V) VCC applications, but with the capability to pro-vide a TTL interface to a 5V environment. The LVT16245and LVTH16245 are fabricated with an advanced BiCMOStechnology to achieve high speed operation similar to 5VABT while maintaining low power dissipation.

Features

sInput and output interface capability to systems at 5V VCCsBushold data inputs eliminate the need for externalpull-up resistors to hold unused inputs (74LVTH16245),also available without bushold feature (74LVT16245).sLive insertion/extraction permitted

sPower Up/Down high impedance provides glitch-freebus loadingsOutputs source/sink 󰀐32 mA/󰀎64 mA

sFunctionally compatible with the 74 series 16245sLatch-up performance exceeds 500 mAsESD performance:

Human-body model !2000VMachine model !200VCharged-device !1000V

sAlso packaged in plastic Fine-Pitch Ball Grid Array(FBGA) (Preliminary)

Ordering Code:

Order Number74LVT16245GX(Note 1)

74LVT16245MEA(Note 2)

74LVT16245MTD(Note 2)

74LVTH16245GX(Note 1)

74LVTH16245MEA(Note 2)

74LVTH16245MTD(Note 2)

Package NumberBGA54A(Preliminary)MS48AMTD48BGA54A(Preliminary)MS48AMTD48

Package Description

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide[Tape and Reel]

48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300\" Wide48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide[Tape and Reel]

48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300\" Wide48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Note 1: BGA package available in Tape and Reel only.

Note 2: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol

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74LVT16245 • 74LVTH16245Connection Diagrams

Pin Assignment for SSOP and TSSOP

Pin Descriptions

Pin NamesOEnT/RnA0–A15B0–B15NC

Description

Output Enable Input (Active LOW)Transmit/Receive InputSide A Inputs/3-STATE OutputsSide B Inputs/3-STATE OutputsNo Connect

FBGA Pin Assignments

1

ABCDEFGHJ

B0B2B4B6B8B10B12B14B15

2NCB1B3B5B7B9B11B13NC

3T/R1NCVCCGNDGNDGNDVCCNCT/R2

4OE1NCVCCGNDGNDGNDVCCNCOE2

5NCA1A3A5A7A9A11A13NC

6A0A2A4A6A8A10A12A14A15

Truth Tables

Inputs

Pin Assignment for FBGA

OE1LLHInputsOE2LLH

(Top Thru View)

T/R2LHX

Outputs

Bus B8–B15 Data to Bus A8–A15Bus A8–A15 Data to Bus B8–B15HIGH–Z State on A8–A15,B8–B15

T/R1LHX

Outputs

Bus B0–B7 Data to Bus A0–A7Bus A0–A7 Data to Bus B0–B7HIGH–Z State on A0–A7,B0–B7

H HIGH Voltage LevelL LOW Voltage LevelX Immaterial

Z High Impedance

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74LVT16245 • 74LVTH16245Functional Description

The LVT16245 and LVTH16245 contain sixteen non-inverting bidirectional buffers with 3-STATE outputs. The device is bytecontrolled with each byte functioning identically, but independent of the other. The control pins can be shorted together toobtain full 16-bit operation.

Logic Diagrams

Note: Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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74LVT16245 • 74LVTH16245Absolute Maximum Ratings(Note 3)

SymbolVCCVIVOIIKIOKIOICCIGNDTSTG

Parameter

Supply VoltageDC Input VoltageOutput VoltageDC Input Diode CurrentDC Output Diode CurrentDC Output Current

DC Supply Current per Supply PinDC Ground Current per Ground PinStorage Temperature Range

Value

Conditions

UnitsVV

Output in 3-STATE

Output in HIGH or LOW State (Note 4)VI 󰀟 GNDVO 󰀟 GND

Output at HIGH State, VO ! VCCOutput at LOW State, VO ! VCC

VmAmAmAmAmA

󰀐0.5 to 󰀎4.6󰀐0.5 to 󰀎7.0󰀐0.5 to 󰀎7.0󰀐0.5 to 󰀎7.0󰀐50󰀐5064128

r64r128󰀐65 to 󰀎150

qC

Recommended Operating Conditions

SymbolVCCVIIOHIOLTA

Supply VoltageInput Voltage

HIGH-Level Output CurrentLOW-Level Output CurrentFree-Air Operating Temperature

Input Edge Rate, VIN 0.8V–2.0V, VCC 3.0V

Parameter

Min2.70

Max3.65.5

UnitsVVmAmA

󰀐3264

󰀐400

󰀎8510

qCns/V

't/'VNote 3: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditionsbeyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.Note 4: IO Absolute Maximum Ratings must be observed.

DC Electrical Characteristics

SymbolVIKVIHVILVOH

Parameter

Input Clamp Diode VoltageInput HIGH VoltageInput LOW VoltageOutput HIGH Voltage

VCC(V)2.72.7–3.62.7–3.62.7–3.62.73.0

VOL

Output LOW Voltage

2.72.73.03.03.0

II(HOLD)(Note 5)II(OD)(Note 5)II

Bushold Input Over-DriveCurrent to Change StateInput Current

Control PinsData Pins

IOFFIPU/PDIOZLIOZL (Note 5)

Power Off Leakage CurrentPower Up/Down 3-STATE Output Current

3-STATE Output Leakage Current3-STATE Output Leakage CurrentBushold Input Minimum Drive

3.03.03.63.63.600–1.53.63.6

75󰀐75500󰀐500

10r1󰀐51r100r100󰀐5󰀐5

PAPAPAPAPA

VCC 󰀐 0.22.42.0

0.20.50.40.50.55

PAPAVV

2.0

0.8

TA 󰀐40qC to 󰀎85qCMin

Max󰀐1.2

UnitsVVV

Conditions

II 󰀐18 mAVO d 0.1V orVO t VCC 󰀐 0.1VIOH 󰀐100 PAIOH 󰀐8 mAIOH 󰀐32 mAIOL 100 PAIOL 24 mAIOL 16 mAIOL 32 mAIOL 64 mAVI 0.8VVI 2.0V(Note 6)(Note 7)VI 5.5VVI 0V or VCCVI 0VVI VCC

0V d VI or VO d 5.5VVO 0.5V to 3.0VVI GND or VCCVO 0.5VVO 0.0V

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74LVT16245 • 74LVTH16245DC Electrical Characteristics (Continued)

SymbolIOZHIOZH (Note 5)IOZH󰀎ICCHICCLICCZICCZ󰀎'ICC(Note 8)

Note 5: Applies to bushold versions only (74LVTH16245).

Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH.Note 7: An external driver must sink at least the specified current to switch from HIGH-to-LOW.

Note 8: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.

Parameter

3-STATE Output Leakage Current3-STATE Output Leakage Current 3-STATE Output Leakage CurrentPower Supply CurrentPower Supply CurrentPower Supply CurrentPower Supply Current

Increase in Power Supply Current

VCC(V)3.63.63.63.63.63.63.63.6

TA 󰀐40qC to 󰀎85qCMin

Max55100.195.00.190.190.2

UnitsPAPAPAmAmAmAmAmA

VO 3.0VVO 3.6V

Conditions

VCC 󰀟 VO d 5.5VOutputs HIGHOutputs LOWOutputs DisabledVCC d VO d 5.5V,Outputs DisabledOne Input at VCC 󰀐 0.6VOther Inputs at VCC or GND

Dynamic Switching Characteristics (Note 9)

SymbolVOLPVOLV

Parameter

Quiet Output Maximum Dynamic VOLQuiet Output Minimum Dynamic VOL

VCC(V)3.33.3

Min

TA 25qCTyp0.8󰀐0.8

Max

UnitsVV

ConditionsCL 50 pF, RL 500:

(Note 10)(Note 10)

Note 9: Characterized in SSOP package. Guaranteed parameter, but not tested.

Note 10: Max number of outputs defined as (n). n󰀐1 data inputs are driven 0V to 3V. Output under test held LOW.

AC Electrical Characteristics

TA 󰀐40qC to 󰀎85qC

Symbol

Parameter

CL 50 pF, RL 500:

VCC 3.3V r 0.3VMin

tPLHtPHLtPZHtPZLtPHZtPLZtOSHLtOSLH

Output to Output Skew(Note 11)

Output Disable TimeOutput Enable Time

Propagation Delay Data to Output

1.51.31.51.62.32.2

Max3.53.54.55.35.45.11.0

VCC 2.7VMin1.51.31.51.62.32.2

Max3.93.95.36.96.15.41.0

nsnsnsnsUnits

Note 11: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. Thespecification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.

Capacitance (Note 12)

SymbolCINCI/O

Parameter

Input CapacitanceInput/Output Capacitance

Conditions

VCC 0V, VI 0V or VCCVCC 3.0V, VO 0V or VCC

Typical48

UnitspFpF

Note 12: Capacitance is measured at frequency f 1 MHz, per MIL-STD-883, Method 3012.

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74LVT16245 • 74LVTH16245Physical Dimensions inches (millimeters) unless otherwise noted

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

Package Number BGA54A

Preliminary

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74LVT16245 • 74LVTH16245Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300\" Wide

Package Number MS48A

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74LVT16245 • 74LVTH16245 Low Voltage 16-Bit Transceiver with 3-STATE OutputsPhysical Dimensions inches (millimeters) unless otherwise noted (Continued)

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Package Number MTD48

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied andFairchild reserves the right at any time without notice to change said circuitry and specifications.LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILDSEMICONDUCTOR CORPORATION. As used herein:1.Life support devices or systems are devices or systemswhich, (a) are intended for surgical implant into thebody, or (b) support or sustain life, and (c) whose failureto perform when properly used in accordance withinstructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to theuser.www.fairchildsemi.com

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2.A critical component in any component of a life supportdevice or system whose failure to perform can be rea-sonably expected to cause the failure of the life supportdevice or system, or to affect its safety or effectiveness.

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